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Integrated Circuit Systems, Inc.
ICS93712
Advance Information
2 DIMM DDR Fanout Buffer
Recommended Application: DDR fan out buffer for VIA PRO 266 DDR chipset Product Description/Features: Low skew, fanout buffer 1 to 6 differential clock distribution I2C for functional and output control Feedback pin for input to output synchronization Supports up to 2 DDR DIMMs Frequency support for up to 400MHz DDR, SDRAMs CMOS level control signal input Switching Characteristics: OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time for DDR outputs: 650ps - 950ps DUTY CYCLE: 47% - 53% Pulse Skew: <100ps
Pin Configuration
FBOUT GND DDRT0 DDRC0 VDD2.5 GND DDRT1 DDRC1 VDD2.5 BUF_IN GND DDRT2 DDRC2 VDD2.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND DDRT5 DDRC5 VDD2.5 GND DDRT4 DDRC4 VDD2.5 GND DDRT3 DDRC3 VDD2.5 SCLK SDATA
28-Pin SSOP
Block Diagram
FB_OUT
BUF_IN
DDRT0 DDRC0 DDRT1 DDRC1
SCLK SDATA
Control Logic
DDRT1 DDRC2 DDRT3 DDRC3 DDRT4 DDRC4 DDRT5 DDRC5
93712 Rev - 9/08/00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS93712
ICS93712
Advance Information Pin Descriptions
PIN NUMBER 1 5, 9, 14, 17, 21, 25 2, 6, 11, 20, 24, 28 27, 23, 19, 12, 7, 3 26, 22, 18, 13, 8, 4 10 15 16 FB_OUT VDD2.5 GND DDRT (5:0) DDRC (5:0) BUF_IN SDATA SCLK P I N NA M E TYPE OUT PWR PWR OUT OUT IN I/O IN DESCRIPTION Feedback output, dedicated for external feedback 2.5V voltage supply Ground "True" Clock of differential pair outputs. "Complementory" clocks of differential pair outputs. Single ended buffer input Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input
Byte 1: Reserved Register (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Bit 7 1 R e s e r ve d Bit 6 1 R e s e r ve d Bit 5 1 R e s e r ve d Bit 4 1 R e s e r ve d Bit 3 1 R e s e r ve d Bit 2 1 R e s e r ve d Bit 1 1 R e s e r ve d Bit 0 1 R e s e r ve d
Byte 2: Reserved Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Byte 3: Reserved Register (1= enable, 0 = disable)
Byte 4: Reserved Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
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ICS93712
Advance Information
Byte 5: Reserved Register (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Byte 6: Output Control (1= enable, 0 = disable) BIT PIN# PWD Bit 7 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 1 Bit 2 27, 26 1 Bit 1 23, 22 1 Bit 0 19, 18 1
DESCRIPTION (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)* DDRT5, DDRC5 DDRT4, DDRC4 DDRT3, DDRC3
Byte 7: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 12, 13 7, 8 3, 4
PWD DESCRIPTION 1 R e s e r ve d * 1 R e s e r ve d * 1 R e s e r ve d * DDRT2 1 DDRC2 1 Reserved* DDRT1 1 DDRC1 1 R e s e r ve d * 1 DDRT0, DDRC0
Note: * For lower power consumption, these bits should be driven to 0.
Switching Characteristics
PARAMETER Maximum Operating Frequency Input clock duty cycle Output to Output Skew Pulse skew Duty cycle Rise Time, Fall Time SYMBOL dtin Tskew Tskewp DC2 tr, tf 66MHz to 100MHz 101MHz to 167MHz Load = 120/16pF CONDITION MIN 66 40 TYP MAX 200 60 100 100 52 53 950 UNITS MHz % ps ps % % ps
48 47 650
Notes: 1. Refers to transition on noninverting output. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up.
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ICS93712
Advance Information Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND 0.5 V to VDD +0.5 V 0C to +85C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Ele ctrical Characte ristics - Input/Supply /Com m on Output Param e te rs
T A = 0 - 85C; Supply Voltage VDD = 2.5 V +/- 0.2V (unless otherwise stated) SYMBOL IIH IIL IDD2 .5 Operating Supply Current IDDPD Output High Current IOH Output Low Current High-level output voltage IOL PARAM ETER Input High Current Input Low Current CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf CL = 0pf VDD = 2.3V, VOUT = 1V VDD = 2.3V, VOUT = 1.2V VDD = min to max, IOH = -1 mA VDD = 2.3V, IOH = -12 mA VDD = min to max IOL=1 mA VDD = 2.3V IOH=12 mA VI = GND or VDD M IN TYP M AX UNITS A A mA A mA mA V V 0.1 0.6 2 V pF
100 -18 26
VOH
Low-level output voltage Input Capacitance 1
1
VOL C IN
Guaranteed by design, not 100% tested in production.
Re com m e nde d Ope rating Condition
T A = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAM ETER Power Supply Voltage Input High Voltage Input Low Voltage Input voltage level Output differential-pair crossing voltage
1
SYM BOL VDD V IH V IL V IN VOC
CONDITIONS
M IN 2.3
TYP 2.5
M AX 2.7
UNITS V V V V V
OE input OE input
Guaranteed by design, not 100% tested in production.
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ICS93712
Advance Information General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controlle r (Host) Start Bit Address D2(H ) Dummy Command Code A CK Dummy Byte Count A CK Byte 0 A CK Byte 1 A CK Byte 2 A CK Byte 3 A CK Byte 4 A CK Byte 5 A CK Byte 6 A CK Byte 7 A CK Stop Bit ICS (Sla ve/Re ceiver)
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit

How to Read:
Controlle r (Host) Start Bit Address D3(H ) ICS (Slave/Rece ive r)
A CK
ACK
A CK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
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ICS93712
Advance Information
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 1.65 0.22 2.00 1.85 0.38 .002 .065 .009 .079 .073 .015
A A1 A2 b c D E E1 e L N VARIATIONS N 28
0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0 8
.0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0 8
D mm. MIN 9.90 MAX 10.50 MIN .390
D (inch) MAX .413
6/1/00 Rev B
MO-150 JEDEC Doc.# 10-0033
Ordering Information
ICS93712yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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